IEEE Solid-State Circuits Letters · 2020 · 22 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignDigital Integrated Circuit DesignDynamic Power ReductionIntegrated Circuit DesignLow-power Digital Circuit DesignPower ManagementCmos Logic CircuitsEnergy ConsumptionEnergy-efficient Digital CircuitsLow-power Cmos DesignLow-power Logic DesignMultiplier DesignSiliconUltra-low-power Cmos
The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16 × 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.
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Ramiro Taco, Itamar Levi, Marco Lanuzza et al. · IEEE Journal of Solid-State Circuits · 2018 · 37 citations
Engineering, Computer Engineering, Electrical Engineering +17