Publication | Closed Access
A 3-to-40-V Automotive-Use GaN Driver With Active Bootstrap Balancing and <i>V</i> <sub>SW</sub> Dual-Edge Dead-Time Modulation Techniques
40
Citations
11
References
2020
Year
Electrical EngineeringEngineeringActive Bootstrap BalancingGan Power SwitchesPower DeviceGan Driver OperatingActive BootstrapPower Semiconductor DeviceGan Power DevicePower Electronic SystemsAutomotive ElectronicsPower ElectronicsElectric DriverPower Electronic Devices
This article presents a GaN driver operating at a switching frequency variable from 10 to 30 MHz to achieve reliable and efficient power conversion for automotive electronics applications. An active bootstrap (BST) balancing (ABB) technique is presented to stabilize the BST rail voltage by sensing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> and controlling BST rail charging. Meanwhile, a V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> dual-edge dead-time (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> ) modulation senses instant V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">IN</sub> and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and generates optimal t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SW</sub> trailing and leading edges, achieving zero-voltage switching (ZVS) turn-on for GaN power switches. To operate at high frequency and retain high efficiency, pulse-based dynamic upand down-level shifters are developed to achieve sub-nanosecond propagation delay with a quiescent current of 0.5 μA. To validate this work, a switching power converter prototype is implemented using a 0.35-μm highvoltage (HV) BCD process. It maintains a constant 5.1-V BST rail voltage to prevent GaN FET from destructive breakdown and accomplishes 0.9-to-3.7-ns t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dead</sub> and 3.7-to-10.4-ns tdead for VSW trailing and leading edge, respectively, in response to load current I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> change from 0.01 to 1.2 A. The proposed techniques jointly improve the efficiency by 8.3%, which peaks at 90.7% for 12-to-5-V conversion and 88% for 40-to-5-V conversion.
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