A 0-dB STF-Peaking 85-MHz BW 74.4-dB SNDR CT ΔΣ ADC With Unary-Approximating DAC Calibration in 28-nm CMOS

Abstract

This article presents a continuous-time (CT) ΔΣ analog-to-digital converter for wireless communication systems with a high tolerance against blockers. The zero-cancellation technique is introduced to eliminate the peaking in the signal transfer function (STF) to achieve better out-of-band-blocker immunity. An on-chip unary-approximating calibration is implemented to calibrate the mismatch of the outer current-steering digital-to-analog converter. A discrete-time (DT) second-order noise-shaping (NS) 2b/cycle asynchronous successive-approximation-register (ASAR) quantizer further reduces the quantization noise and the excess loop delay, achieving a CT-DT hybrid sixth-order NS without suffering from neither the problem of the CT-DT transfer function matching in a CT multistage NS topology nor the stability issue in a singleloop fully CT sixth-order topology. The prototype is fabricated in 28-nm bulk CMOS and is clocked at 1.7 GHz. With a bandwidth of 85 MHz, the analog-to-digital converter achieves 0-dB peaking STF, 74.4-dB signal to noise and SNDR and 87.5-dB spuriousfree dynamic range, while consuming 61.8-mW power, resulting in an excellent Schreier Figure-of-Merit (FoMS) of 165.8 dB.