CMOS-integrated nanoscale memristive crossbars for CNN and optimization acceleration

Abstract

While memristive crossbars have been reported to offer substantial performance efficiency benefits orders of magnitude above digital processors, there remain high risks in analog computing platforms using emerging non-volatile memory technologies, primarily due to device performance, variability, yield, and interactions with peripheral circuits. We directly integrated CMOS and nanoscale (down to 25 nm) memristors for fully on-chip reading/programming/computing demonstrations. We operate in a low power regime, program with fine control, showing high yield and low variability across our memristive arrays. With the integrated chip, we successfully demonstrated a multi-layer convolutional neural network with MNIST classification accuracy of above 95.3%, demonstrating several concepts in proposed architectures for hybrid analog-digital computing. The ability to tackle NP-hard optimization problems is also experimentally demonstrated with this platform. This work de-risks many of the chief concerns for an accelerator based on analog rather than purely digital computing circuits, as well as validating the core elements of a future in-memory computing architecture.