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Track-and-Zoom Neural Analog-to-Digital Converter With Blind Stimulation Artifact Rejection
69
Citations
34
References
2020
Year
EngineeringAnalog DesignNeuromodulation TherapiesModulator Feedback DacSocial SciencesSlow PotentialsNeuromodulationMixed-signal Integrated CircuitNeurologyMotor NeurophysiologyAnalog-to-digital ConverterEnergy ConsumptionAnalog System EngineeringComputer EngineeringSensorimotor IntegrationNeural InterfaceBrain-computer InterfaceNeuroengineeringNeurophysiologyBrain ElectrophysiologyNeuroscienceElectrophysiology
Closed-loop neuromodulation for the treatment of neurological disorders requires monitoring of the brain activity uninterruptedly even during neurostimulation. This article presents a bidirectional 32-channel CMOS neural interface that can record neural activity during stimulation. Each channel consists of a dc-coupled Δ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Σ-modulated analog-to-digital converter (neural-ADC), which records slow potentials (<; 0.1 Hz) while accommodating rail-to-rail dc offset using a spectrum-shaping front-end. This front-end equalizes the neural signal spectrum before signal quantization, which reduces the energy consumption and silicon area. Upon detection of a large artifact by an in-channel event-triggered digital block, the modulator feedback DAC tracks the artifact with step sizes incrementing in a radix-2 exponential form, preventing the neural-ADC from saturation. Upon tracking the artifact, the multi-bit DAC step size is reduced to zoom into the input neural signal at the highest recording resolution. The modulator's multi-bit DAC is reused in a time-shared fashion as a current-mode stimulator with no area overhead. The Δ <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Σ-ADC consumes 1.7 μW from 0.6-V/1.2-V digital/analog supplies and time-shares the modulator's feedback DAC as the multi-bit current-mode stimulator operating at 3.3 V. The ADC occupies a silicon area of 0.023 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> in the 130-nm CMOS and achieves a signal-to-noise-and-distortion ratio (SNDR) of 70 dB over the 500-Hz bandwidth and an equivalent noise efficiency factor (NEF) of 2.86 without a stand-alone front-end amplifier. The 32-channel bidirectionally interfacing prototype is validated in the in vivo whole brain of a rodent.
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