16.7 A 40MHz-BW 76.2dB/78.0dB SNDR/DR Noise-Shaping Nonuniform Sampling ADC with Single Phase-Domain Level Crossing and Embedded Nonuniform Digital Signal Processor in 28nm CMOS

Abstract

A low-power, wide-bandwidth, and high-dynamic-range (DR) ADC is one of the critical building blocks in a wireless receiver design, in which a continuous-time delta-sigma modulator (CT DSM) has become a popular choice. However, the demand for a wider bandwidth has increased the sampling rate, F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> , which requires high-speed and highly linear analog building blocks, and excess loop delay compensation (ELDC) [1]. Reducing the over-sampling ratio can relax these requirements, but it results in more quantization levels and high-order noise shaping (NS). The feedback DAC often becomes a design challenge, as its distortion degrades ADC performance and can require linearization and higher supply voltage [2]-[4]. To avoid these issues, this work proposes a voltage-controlled oscillator (VCO)-based noise-shaping nonuniform sampling (NUS) ADC architecture, including an NUS modulator and a nonuniform digital signal processor (NU DSP). By leveraging the unique property of NUS [5], the spectral aliasing on the quantization error is independent of the actual average sampling rate, F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> . Thus, the quantization error can be shaped to a frequency much higher than F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s,</sub> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">avg</sub> and later filtered by NU DSP. Achieving similar SNDR as CT DSM, the proposed architecture only requires first-order NS, enabling open-loop architecture without stability and ELD issues. The NUS modulator is mostly digital architecture without amplifiers, a reference voltage generator, and DACs, which is suitable for technology scaling. A proof-of-concept prototype has been fabricated in 28nm CMOS, achieving a peak SNDR/DR of 76.2dB/78.0dB over a 40MHz BW with a Walden FoMw of 41.5fJ/conv-step and a Schreier FoMs of 169.8dB/171.6dB (in SNDR/DR). To the best of the authors' knowledge, this is the first NS ADC prototype to integrate both an NUS modulator and an NU DSP on chip, generating uniform digital outputs from nonuniformly sampled analog input signals.