9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration

Abstract

The noise-shaping SAR (NS-SAR) hybrid architecture has shown its potential in achieving tens of MHz bandwidth (BW) together with high resolution [1]-[2]. However, in [1], the performance is debilitated by the passive 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -order NS, thus limiting the achievable SNDR below 70dB; while with an NS order as high as 4 for SNDR > 70dB based on the interleaving structure [2], power-hungry preamplifiers are essential for residue summation and low-noise targets, which in consequence restricts its Schreier FoM (FoMs) to 166dB. Whereas the 0-1 MASH SDM based on the pipeline-SAR structure retains an FoMs > 170dB [3], the speed of this single-channel ADC is confined by the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -stage with the BW of 12.5MHz, and its power-hungry residue amplifier (RA) occupies> 70% of the total ADC power. Besides, its inter-stage offset and gain mismatch are only foreground calibrated, thus suffering from VT variations. Last but not least, it accommodates an area-hungry bit weight calibration to ensure the DAC linearity. In the presented SAR-assisted NS pipeline ADC, a 2-input-pair dynamic amplifier is used for both pipeline operation and error feedback (EF) residue summation, thereby ensuring good power efficiency overall. Besides, a partial interleaving (PI) structure is adopted to relieve the speed constraint from the 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -stage, which also allows introducing DWA to the PI-DACs without extra timing overhead.