A Digitally-Calibrated 70.98dB-SNDR 625kHz-Bandwidth Temperature-Tolerant 2^nd-order Noise-Shaping SAR ADC in 65nm CMOS

Abstract

This paper presents a temperature-tolerant 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nd</sup> -order noise-shaping (NS) SAR ADC employing a cascade of a temperature-compensated dynamic amplifier and a ring amplifier to realize a low-power/low-noise feedback path gain. A new mismatch calibration technique optimized for a noise-shaping SAR ADC is also presented. Fabricated in 65nm CMOS, the prototype ADC shows peak SNDR of 70.98dB with a signal bandwidth of 625kHz. Over 70-degree of the temperature range, it shows only 2dB SNDR drop. With a total power consumption of 130 μW, it achieves Walden FoM of FoMW=35.9f and Schreier FoM of FoMS=168dB, respectively.