Development of a Generic and a Reconfigurable UVM-Based Verification Environment for SoC Buses

Abstract

The similarities between SoC buses depends partially but not totally on domain. Generic universal verification methodology (UVM) architectures can be used to reduce effort and time to market. Generic UVM allows focusing on test cases rather than building the UVM. Although there are common features between SoC buses, but some properties and test cases must be customized. This paper presents a generic and reusable verification environment for SoC buses to accelerate verification process. To evaluate the efficiency of the proposed methodology, we apply it to three different SoC buses. The results are very promising in terms of high reusability and reducing of verification time.