Fabrication technique of the Si _0.5 Ge _0.5 Fin for the high mobility channel FinFET device

Abstract

Abstract In this paper, a fabrication technique of Si 0.5 Ge 0.5 Fin for the high mobility channel FinFET device is systematically investigated. Although the shallow trench isolation (STI) densification temperature is already reduced from 1050 °C to 850 °C, the Si 0.5 Ge 0.5 Fin with the STI annealing first approach still suffers from thermal instability and micro trench issue. It is no possible to further reduce the STI densification temperature using the traditional furnace annealing for the Si 0.5 Ge 0.5 Fin, because the STI densification process of 750 °C also faces the same issue with an unacceptable STI wet etching rate. Thus, a spike annealing of 1050 °C is employed to maintain Si 0.5 Ge 0.5 Fin stability and render the STI etching rate acceptable. The spike annealing treated Si 0.5 Ge 0.5 Fin maintains a better profile than the furnace annealing sample, but it still faces the micro trench issue after the STI recess. This is because the Si 0.5 Ge 0.5 Fin is already oxidized and SiGeO x has a higher etching rate than STI oxide. Finally, a novel STI recess first process with an extra SiN capping is developed to solve both the thermal instability and the micro trench issue, and a minor Si 0.5 Ge 0.5 Fin loss with sharp Si 0.7 Ge 0.3 SRB/Si 0.5 Ge 0.5 interfaces for the STI last scheme is realized by utilizing this novel STI recess first process.