Towards 10000TOPS/W DNN Inference with Analog in-Memory Computing – A Circuit Blueprint, Device Options and Requirements

Abstract

This paper presents a blueprint for a 10000TOPS/W matrix-vector multiplier for neural network inference based on Analog in-Memory Computing (AiMC), an energy efficiency at least 10x beyond ultimate digital implementations. The presented analysis connects circuit design with technology options and requirements. A compute array using pulse-width encoded activations and precharge-discharge summation line is used as circuit blueprint, key device requirements for this compute array are derived and 3 suited device options are discussed: SOT-MRAM, IGZO-based 2T1C DRAM gain cell, and projection PCM with separate write path.