Performance of Junctionless and Inversion-Mode Thin-Film Transistors With Stacked Nanosheet Channels

Abstract

This article comprehensively investigated a junctionless thin-film transistor (JL TFT) with stacked nanosheet (NS) channels. Through experiments, we 1) compared a JL TFT with a single NS channel and a JL TFT with stacked NS channels and 2) compared an inversion-mode TFT with stacked NS channels and the JL TFT with stacked NS channels; the TFTs were fabricated using Si-based technology. The JL TFT with stacked NS channels exhibited a subthreshold slope of 135 mV/dec and drain-induced barrier-lowering value of 50.8 mVV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , which were superior to those of the other devices. Furthermore, we simulated another device with a hybrid P/N/P channel structure based on the JL TFT by using three-dimensional technology computer aided design (3D TCAD) simulation. According to the study results, the JL TFT with stacked NS channels is a promising candidate for scaling down Si TFTs and for use in advanced 3D applications.