FPGA Implementation of the Real-Time ADTF process using the Intel-Altera DE1 Board for ECG signal Denoising

Abstract

The aim of this paper is to propose an FPGA implementation of the real-time ADTF architecture of the ECG signal denoising based on the DE1 board of Intel-Altera. The results of the proposed implementation as well as the comparative study of this implementation in some different low-cost FPGA architectures show that the proposed FPGA implementation of the real-time ADTF architecture presents an efficient and optimized hardware solution for the real-time ECG signal denoising in different sorts of the low-cost FPGA architectures.