STICKS - A graphical compiler for high level LSl design.

Abstract

The need for good design automation in the area of integrated circuit layout is severe. It is believed that the STICKS system does much to fill that need. STICKS is a computer aided design system which frees the designer from the tedious aspects of IC design and allows him to concentrate on the more creative and necessarily human side of the design process. With STICKS the designer is allowed to divorce himself from the usual precise sizes, spacings, and interrelationships required for an IC layout and, instead, submit his creativity in the form of rough, freehand sketches. The computer makes whatever adjustments are necessary in order to generate an error-free layout. The opportunity is then given to verify and, if necessary, modify the computer's interpretation of the design .. An interactive loop is thus formed with the computer doing all of the tedious, detailed work and the human designer providing the necessary inspiration. Using traditional' methods, large scale integrated circuit layout is a tedious, time consuming and error prone process. IC layout is a procedure which results in the placement and interconnection of each of the thousands of components which . form the integrated circuit. The designer accomplishes this by drawing several superimposed mask layers using a drafting board which together, control the areas where various chemical diffusions and etchings will be made on the silicon wafer that forms the IC. Components such as transistors, diodes, resistors, and their interconnections are formed by various combinations of these masked areas. Unfortunately, the specific sizes of and spacings between components is critical, preventing the designer's job from being an easy one. There is an overall goal in IC design to pack as much circuitry as possible into a small area. The more circuitry a particular IC contains, the more valuable it is and, consequently, the more marketable it is. The physical size of the chip, however, is a major factor constraining the number of components. Due to a parameter known as defect density, the larger the chip, the less likely it is to work and the more it will cost. Defect density is the number of random material defects per given area which result both from the starting silicon material and from normal losses in the manufacturing process. The solution, one would think, would be to simply make everything smaller thereby increasing component den-