Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET - Concepedia

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Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET

44

Citations

21

References

2019

Year

Yunho Choi, Kitae Lee, Kyoung Yeon Kim, Sihyun Kim, Junil Lee, Ryoongbin Lee, Hyun‐Min Kim, Young Suh Song, Sangwan Kim, Jong‐Ho Lee,

Solid-State Electronics

Device ModelingElectrical EngineeringSemiconductor DeviceEngineeringNanoelectronicsNanotechnologyBias Temperature InstabilityApplied PhysicsSemiconductor Device FabricationMicroelectronicsParasitic Channel

References

	Year	Citations

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