A 9 dB Noise Figure Fully Integrated 79 GHz Automotive Radar Receiver in 40 nm CMOS Technology

Abstract

This paper presents a low noise and fully integrated automotive radar receiver in 40 nm CMOS technology. The receiver adopts the direct conversion architecture, and it consists of a low noise amplifier (LNA), mixer, and analog baseband blocks. The three-stage LNA and the low noise mixer improve the whole receiver noise figure (NF). Integrated low-dropped out regulators (LDOs) generate 1.1 V for the LNA and the mixer core from 1.8 V supply. The receiver chip also includes a frequency doubler, phase-locked loop (PLL), bandgap reference bias circuit, and a serial peripheral interface (SPI). The die is packaged using the wafer level chip size package (WLCSP). The receiver achieves 9.0 dB NF at 81 GHz local (LO) and 76.8 dB maximum gain. Moreover, the receiver front-end shows -22.3 dBm IP1dB, and consumes 143 mW power dissipation, and 0.8 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area.