1 Kbit 6T SRAM Arrays in Carbon Nanotube FET CMOS

Abstract

We experimentally demonstrate the first static random-access memory (SRAM) arrays based on carbon nanotube (CNT) field-effect transistors (CNFETs). We demonstrate full 1 Kbit 6 transistor (6T) SRAM arrays fabricated with CNFET CMOS (totalling 6,144 p-and n-type CNFETs), with all 1,024 cells functioning correctly without any per-unit customization. We demonstrate robust operation by writing and reading multiple patterns to the Kbit arrays and characterize single-cell SRAM variability (write and read margins) and repeat cycling of cells. Due to low-temperature BEOL-compatible processing, CNFET SRAM enables new opportunities for digital systems, since: (1) CNFET SRAM can be fabricated directly on top of computing logic, and (2) buried power rails (i.e., as in our demonstration where the power rails are fabricated underneath the FET) can potentially enable smaller-area SRAM layouts.