2019 · 19 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureInterconnection NetworksVlsi DesignInterconnect ArchitectureInterconnect DesignNetwork-on-chip DesignProcessor Core DesignRoutingRouting ArchitectureBandwidthManycore ArchitecturesNetwork-on-chipNetwork-on-chip ArchitecturesOn-chip NetworksRisc ArchitecturesRisc-v Core DesignScalable Interconnects
This paper presents a 16 nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.