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A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS
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2019
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System On ChipElectrical EngineeringManycore ProcessorEngineeringVlsi DesignAggregate BandwidthRouter ArchitectureMany-core ArchitectureComputer ArchitectureComputer EngineeringNetwork On ChipMesh On-chip NetworkRouter DesignParallel ComputingCoremark Benchmark ScoreMicroelectronicsAll-digital Synthesized PllNoc Architecture
This paper presents a 16 nm 496-core RISC-V network-on-chip (NoC). The mesh achieves 1.4 GHz at 0.98 V, yielding a peak of 695 Giga RISC-V instructions/s (GRVIS) and a record 812,350 CoreMark benchmark score. The main feature is the NoC architecture, which uses only 1881 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> per router node, enables highly scalable and dense compute, and provides up to 361 Tb/s of aggregate bandwidth.