IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019 · 135 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureCryptographyField-programmable Gate ArraysConfigurable Logic BlocksField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationLattice-based CryptographyPost-quantum CryptographyArithmetic Logic Unit ArchitectureCryptographic AccelerationCryptographic Accelerator DesignField-programmable Gate Array AccelerationHardware Acceleration For CryptographyParallel OperationsPost-quantum Cryptography ImplementationPost-quantum Cryptography Standardization
Lattice-based cryptography (LBC) is one of the most promising classes of post-quantum cryptography (PQC) that is being considered for standardization. This brief proposes an optimized schoolbook polynomial multiplication (SPM) for compact LBC. We exploit the symmetric nature of Gaussian noise for bit reduction. Additionally, a single field-programmable gate array (FPGA) DSP block is used for two parallel multiplication operations per clock cycle. These optimizations enable a significant 2.2× speedup along with reduced resources for dimension n = 256. The overall efficiency (throughput per slice) is 1.28× higher than the conventional SPM, as well as contributing to a more compact LBC system compared to previously reported designs. The results targeting the FPGA platform show that the proposed design can achieve high hardware efficiency with reduced hardware area costs.
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Daniel J. Bernstein, Tanja Lange · Nature · 2017 · 1.1K citations · Full text
Compact and provably secure lattice-based signatures in hardware
James Howe, Ciara Rafferty, Ayesha Khalid et al. · 2017 · 14 citations · Full text