Network architecture for a topological quantum computer in silicon

Abstract

A design for a large-scale surface code quantum processor based on a\nnode/network approach is introduced for semiconductor quantum dot spin qubits.\nThe minimal node contains only 7 quantum dots, and nodes are separated on the\nmicron scale, creating useful space for wiring interconnects and integration of\nconventional transistor circuits. Entanglement is distributed between\nneighbouring nodes by loading spin singlets locally and then shuttling one\nmember of the pair through a linear array of empty dots. Each node contains one\ndata qubit, two ancilla qubits, and additional dots to facilitate electron\nshuttling and measurement of the ancillas. A four-node GHZ state is realized by\nsharing three internode singlets followed by local gate operations and ancilla\nmeasurements. Further local operations and measurements produce an X or Z\nstabilizer on four data qubits, which is the fundamental operation of the\nsurface code. Electron shuttling is simulated using a simplified gate electrode\ngeometry without explicit barrier gates, and demonstrates that adiabatic\ntransport is possible on timescales that do not present a speed bottleneck to\nthe processor. An important shuttling error in a clean system is uncontrolled\nphase rotation due to the modulation of the electronic g-factor during\ntransport, owing to the Stark effect. This error can be reduced by appropriate\nelectrostatic tuning of the stationary electron's g-factor. Using reasonable\nnoise models, we estimate error thresholds with respect to single and two-qubit\ngate fidelities as well as singlet dephasing errors during shuttling. A\ntwirling protocol transforms the non-Pauli noise associated with exchange gate\noperations into Pauli noise, making it possible to use the Gottesman-Knill\ntheorem to efficiently simulate large codes.\n