Parasitic Inductance Modeling and Reduction for a Wire Bonded Half Bridge SiC MOSFET Multichip Power Module

Abstract

The parasitic inductance in the current commutation loop (CCL) could cause current and voltage oscillations during switching transient, increase switching loss, EMI and voltage stress on power semiconductor devices. These undesirable features intensify with the use of Wide Bandgap (WBG) devices due to increased switching speed and lower on-resistance. In this paper, the parasitic inductance of the current commutation loop is modeled with Partial Element Equivalent Circuit (PEEC) method for SiC multichip module. Different from other studies, the mutual inductance between paralleled branches are thoroughly analyzed and included in the model. As shown in Finite Element Analysis (FEA) simulation and experiment measurement, the mutual inductance has significant influence on the accuracy of the model. A wire bonded package layout is then proposed for SiC multichip half bridge modules that could reduce parasitic inductance without increasing fabrication difficulty. The effectiveness of the developed structure is verified with 3D FEA simulation and experiment.