A 93.4–104.8-GHz 57-mW Fractional-${N}$ Cascaded PLL With True In-Phase Injection-Coupled QVCO in 65-nm CMOS Technology

Abstract

A fully integrated 93.4-104.8-GHz 57-mW fractional-N cascaded phase-locked loop (PLL) with true in-phase injection-coupled quadrature voltage-controlled oscillator (QVCO) is reported. By cascading the fractional-N PLL and the subsampling PLL, good phase noise, high resolution, and wide acquisition range are achieved simultaneously. The transformer-based true in-phase injection coupled technique is adopted in the QVCO to obtain both low phase noise and low-power consumption. The proposed cascaded PLL was fabricated in a 65-nm CMOS technology with silicon size of 0.88 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured phase noise of QVCO and PLL is -113.26 and -106.63 dBc/Hz at 10-MHz offset, respectively. The FOM and FOMT of the QVCO at 10-MHz offset are -178.4 and -180.0 dBc/Hz, respectively. The frequency resolution of the 100-GHz output is less than 3.6 kHz.