2019 · 104 citations · 26 references
ComputingComputer EngineeringComputer ScienceComputer SecurityHardware SecuritySecurity ArchitectureConfigurable Logic BlocksHardware ObfuscationLogic LockingMicroarchitectural SecurityProgrammable Logic DevicesSecurity HardeningHardware Intellectual Property ProtectionIp Piracy PreventionLogic Locking ObfuscationProgrammable Logic DesignRemoval AttacksSat Attack ResistanceSat AttacksSecure Hardware Ip Protection
In this paper, we propose a novel and SAT-resistant logic-locking technique, denoted as Full-Lock, to obfuscate and protect the hardware against threats including IP-piracy and reverse-engineering. The Full-Lock is constructed using a set of small-size fully Programmable Logic and Routing block (PLR) networks. The PLRs are SAT-hard instances with reasonable power, performance and area overheads which are used to obfuscate (1) the routing of a group of selected wires and (2) the logic of the gates leading and proceeding the selected wires. The Full-Lock resists removal attacks and breaks a SAT attack by significantly increasing the complexity of each SAT iteration.
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Parallel Processing with the Perfect Shuffle
Harold S. Stone · IEEE Transactions on Computers · 1971 · 1.3K citations
Where the really hard problems are
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