2019 · 46 citations · 31 references
ComputingComputer EngineeringComputer SystemsEmbedded SystemsInternet Of ThingsMachine LearningAccelerator ArchitectureHardware AccelerationNeural NetworksReconfigurable AcceleratorsSpeech RecognitionSpiking Neural NetworksDeep Learning AcceleratorsGated Recurrent Unit NetworksIot Platform ArchitectureLatency ReductionPower ConsumptionProcessing LatencyRecurrent Neural NetworksThroughput
This paper describes a continuous speech recognition hardware system that uses a delta recurrent neural network accelerator (DeltaRNN) implemented on a Xilinx Zynq-7100 FPGA to enable low latency recurrent neural network (RNN) computation. The implemented network consists of a single-layer RNN with 256 gated recurrent unit (GRU) neurons and is driven by input features generated either from the output of a filter bank running on the ARM core of the FPGA in a PmodMic3 microphone setup or from the asynchronous outputs of a spiking silicon cochlea circuit. The microphone setup achieves 7.1 ms minimum latency and 177 frames-per-second (FPS) maximum throughput while the cochlea setup achieves 2.9 ms minimum latency and 345 FPS maximum throughput. The low latency and 70 mW power consumption of the DeltaRNN makes it suitable as an IoT computing platform.
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Connectionist temporal classification
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Itay Hubara, Daniel Soudry · arXiv (Cornell University) · 2016 · 924 citations · Full text