A Compact pMOS Stacked-SOI Distributed Power Amplifier With Over 100-GHz Bandwidth and Up to 22-dBm Saturated Output Power

Abstract

This letter presents an all-pMOS stacked-SOI distributed power amplifier (DPA) as an alternative to conventional nMOS for higher reliable operating voltages. The pMOS-DPA uses 8-shaped input and output transmission lines (TLs) for magnetic held confinement and a compact chip area. The amplifier operates from 1.5 GHz to greater than 100 GHz using an on-chip 2-section dc-feed, diminishing the need for a bulky external bias-tee. A prototype 8-stage, 16-dB gain, 101-GHz small-signal 3-dB bandwidth all-pMOS DPA is implemented in 45-nm CMOS SOI with a core area of 0.33 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The pMOS design demonstrates an output P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> and P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> higher than 17 and 19 dBm, respectively, and a state-of-the-art PAE higher than 10%, up to 60 GHz, with a 60-GHz P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> 3-dB bandwidth. At 28 GHz, the DPA achieves 30 Gb/s 64-QAM and 8 Gb/s 256-QAM with average P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">out</sub> of 14.5 and 10.2 dBm, respectively. To the authors' knowledge, this is the first implementation of a silicon DA with over 100-GHz bandwidth made exclusively with pMOS. The PA reports the highest 256-QAM data rate (8 Gb/s) for a 10-dBm output power. The pMOS amplifier also has the smallest reported chip area, including the dc-feed for DPAs achieving 500+ GHz GBW.