A 2.3-mW, 1-GHz, 8-Bit Fully Time-Based Two-Step ADC Using a High-Linearity Dynamic VTC

Abstract

A novel fully time-based two-step analog-to-digital converter (ADC) is proposed. Two time-based ADCs (TB ADCs) are used for coarse ADC (CADC) and fine ADC (FADC), resulting in low-power operation. They are pipelined to increase the sampling frequency. A high-linearity voltage-to-time converter is also proposed to ensure that the CADC has a wide input range. It has a gain-control function to adjust the difference between the gains of the CADC and FADC due to variations in process, voltage and temperature. Moreover, an interpolation time-to-digital converter with a dynamic delayer enables low-power operation. The dynamic delayer is immediately reset when a STOP signal is activated to prevent waste-signal propagation. An 8-bit test chip fabricated with the 65-nm CMOS technology consumed 2.3 mW at 1 GS/s. It also had a sufficiently high signal-to-noise and distortion ratio (SNDR) of 44.4 dB even at the Nyquist frequency. It had a Walden figure of merit of 16 fJ/conversion step.