The dual processor platform architecture

Abstract

The Dual Processor Platform (DPP) is a novel architecture template for networked embedded systems based on a strictly asynchronous processor interconnect that allows to minimize interference with a proven predictable behavior [7]. Contrary to traditional platforms [1, 5] DPP tries to mitigate interference by isolating different tasks and mapping them onto dedicated hardware resources. Typically, two different task sets - (i) sensing/actuation/data processing and (ii) communication - are mapped onto two different physically separated processing elements (usually low-power microcontrollers), allowing each to be optimized according to their individual requirements. Such hardware partitioning is a standard approach, frequently found in more complex sensor system implementations [2]. While the communication processor handles wireless packet transmission and reception, the application processor is dedicated to the sensor data acquisition, processing and actuation. But this strict separation of resources and function also requires a processor interconnect: BOLT [7], a stateful processor interconnect specifically designed based on this paradigm allows a strict decoupling of the power, clock and time domains of the two processing elements by allowing only asynchronous message passing between the two. The strict limitation to an asynchronous interface allows for predictable run-time behavior that, in addition to typical behavior observed from experiments, has been formally verified [7]. The most notable advantages of this approach are: