New approach to low-area, low-latency memory-based systolic architecture for FIR filters

Abstract

A new approach to memory based systolic architecture for higher order FIR filter has been proposed. The memory- based multiplier used in this systolic FIR filter design is different from the earlier used memory-based multipliers. This design is applicable for low-area, low latency and high throughput FIR filters. Both 1-D and 2-D systolic computing structures for higher order FIR filter are derived and implemented in Xillinx Virtex-7 XC7vx330tffg1157 FPGA using VHDL. Various performance metrics like number of slices, latency of the filter and maximum frequency of operation of the filter are compared for different filter orders at various input sample length. The parameters are compared for both 1-D and 2-D systolic structure. For a 128-order filter with an input length of 32-bit, the proposed 2-D structure at eighth-level decomposition occupies 88.9% less area as compared to 1-D structure. The latency of the filter is reduced from 127.5ns to 3.5ns for a 128-order filter using the proposed decomposed structure.