A Reconfigurable Transient Optimizer Applied to a Four-Phase Buck Converter for Optimizing Both DVS and Load Transient Responses

Abstract

This brief presents a reconfigurable transient optimizer (RTO) applied to a four-phase buck converter for optimizing both dynamic-voltage-scaling (DVS) and load transient responses to approach the theoretically minimum output-voltage undershootΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">US</sub> , overshoot ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS</sub> , and settling time tS. The DVS and load transients are instantly detected by a voltage sensor and calibrated capacitor-current sensor, respectively. When a large DVS or load transient occurs, the RTO enables all four phases, reconfigures its circuit architecture, and controls the optimal ON-OFF times of the power switches, thereby settling the output voltage in a single ON-OFF switching with ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">US</sub> , ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS</sub> , and tS close to their respective theoretical minima. The converter is fabricated in a 0.18-μm CMOS process with a 2.3-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip area. For a 1-to-1.8 V (1.8-to-1 V) DVS transient, the measured ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS</sub> (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">US</sub> ) is not observable, while the measured tS is 182 ns (192 ns). For a 1.8-A step-up (step-down) load transient, the measured ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">US</sub> (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS</sub> ) and tS are 56 mV (45 mV) and 85 ns (76 ns), respectively. Compared with other state-of-the-arts, this brief's tS in the DVS transient response is the closest to its theoretical minimum, while the ratios of ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">US</sub> , ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OS</sub> , and tS to their respective theoretical minima in the load transient response are comparable.