Scalable Digital Neuromorphic Architecture for Large-Scale Biophysically Meaningful Neural Network With Multi-Compartment Neurons

TLDR

Multicompartment emulation is essential for enhancing biological realism in neuromorphic systems and understanding neuronal computational power. The study presents a hardware‑efficient, scalable, real‑time strategy to implement large‑scale biologically meaningful neural networks with one million multi‑compartment neurons. The authors implement the system on four Altera Stratix III FPGAs, using a cost‑efficient multi‑CMN model that reproduces detailed neuronal dynamics and a scalable NoC architecture with a novel routing algorithm to improve throughput and reduce latency. Experimental results show a 56.59 % speed increase over classical digital implementations, low area utilization, and high computational speed, confirming the approach’s efficiency and scalability for large‑scale biologically meaningful networks.

Abstract

Multicompartment emulation is an essential step to enhance the biological realism of neuromorphic systems and to further understand the computational power of neurons. In this paper, we present a hardware efficient, scalable, and real-time computing strategy for the implementation of large-scale biologically meaningful neural networks with one million multi-compartment neurons (CMNs). The hardware platform uses four Altera Stratix III field-programmable gate arrays, and both the cellular and the network levels are considered, which provides an efficient implementation of a large-scale spiking neural network with biophysically plausible dynamics. At the cellular level, a cost-efficient multi-CMN model is presented, which can reproduce the detailed neuronal dynamics with representative neuronal morphology. A set of efficient neuromorphic techniques for single-CMN implementation are presented with all the hardware cost of memory and multiplier resources removed and with hardware performance of computational speed enhanced by 56.59% in comparison with the classical digital implementation method. At the network level, a scalable network-on-chip (NoC) architecture is proposed with a novel routing algorithm to enhance the NoC performance including throughput and computational latency, leading to higher computational efficiency and capability in comparison with state-of-the-art projects. The experimental results demonstrate that the proposed work can provide an efficient model and architecture for large-scale biologically meaningful networks, while the hardware synthesis results demonstrate low area utilization and high computational speed that supports the scalability of the approach.