Design of an energy-efficient XNOR gate based on MTJ-based nonvolatile logic-in-memory architecture for binary neural network hardware

Abstract

A nonvolatile logic gate based on magnetic tunnel junction-based nonvolatile logic-in-memory (NV-LIM) architecture is designed for the implementation of compact and low-power binary neural network (BNN) hardware. The use of NV-LIM architecture for designing BNN hardware makes it possible to reduce both computational and data transfer costs associated with inference functions of deep neural networks. Through an experimental evaluation of a basic component of BNN hardware designed with NV-LIM architecture, we demonstrate that a nonvolatile logic gate designed and optimized based on its quantitative analysis can reduce the circuit area to 32% of a conventional structure as well as reduce the average power consumption assuming intermittent operation in sensor node applications to 14%.