Design Features of High-Speed CMOS Differential Difference Operational Amplifiers at Low Static Current Consumption

Abstract

In article interrelation of the linear operation range of a CMOS differential difference operational amplifier (DDOA) with the main parameter of the pass characteristics of its input differential stages (DS), the limiting voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">lim</sub> ), is considered. The results of mathematical and comparative computer modeling of the dependence of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">lim</sub> typical CMOS DS on the channel width of transistors at different static currents for three CMOS technological foundry processes (0.25 um SiGe CMOS, 0.35um SiGe CMOS and 0.6 um Si CMOS) are presented. Recommendations are given for increasing the maximum slew rate of the output voltage (SR) of the DDOA, which are based on the introduction into each input DS of a differentiating circuit of transient correction.