CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI

Abstract

Cu interconnects suffer from steep rise in resistivity and severe reliability degradation for sub-20 nm line widths. Other metals, including Co and Ru, have been demonstrated with higher electromigration (EM) resistance, but exhibit lower electrical conductivity that degrades circuit performance. This work reports multilayer graphene (MLG) directly grown on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> substrate at 300 °C by a novel pressure-assisted solid-phase diffusion synthesis method, and, for the first time, demonstrates a CMOS-compatible intercalation doped graphene nanoribbon (DGNR) interconnect technology with smaller electrical resistivity than Cu, Co and Ru interconnects. The DGNR interconnect also exhibits <; 4% conductivity degradation over 1000 hours at room temperature (RT) without any encapsulation or barrier layer, and negligible EM under 100 MA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> current stress test at > 100°C.