An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC

Abstract

This paper presents an 11b 80MS/s successive approximation register (SAR) analog-to-digital converter (ADC) in 65nm CMOS with a speed-enhanced control logic. The accelerated SAR logic leads to more settling time of the capacitive digital-to-analog converter (CDAC) and reduces decoupling capacitance area. A high-linearity CDAC using custom-designed unit capacitor with small interconnection parasitic capacitance is also adopted in this design. With the two techniques, the ADC achieves small die area and good linearity. Measurement results show that the ADC achieves SNDR/SFDR of 60.50/80.93 dB and 55.81/76.10 dB at low and Nyquist input frequency respectively. The ADC core consume s 1.41 mW from 1.2V supply, translating into 20.36 fJ/conversion-step.