Optimized Layer Architecture for Layered LDPC Code Decoder

Abstract

Low Density Parity Check (LDPC) codes have been widely used as error correction codes for many application on communication discipline. It has been proved that they can approach Shannon's capacity limit and implementable. On the other hand, the architecture of LDPC decoders should be designed carefully in order to obtain a convincing trade-off between logic complexity and error correction performance. In this paper, we proposed an optimized Block Processing Unit (BPU) to perform all the operations of check nodes and variable nodes of a QC-LDPC/LDPC decoder. The optimized BPU can reduce the logic complexity significantly compared to the original one. While the same quantization bit-width and calculation are employed, it can maintain a similar throughput and error correction performance. The experimental results show that it can provide a better trade-off between the logic complexity and the error correction performance than the original one.