Impedance Control of a Saturated Core Superconducting Fault Current Limiter With an Improved Field Suppression

Abstract

This paper presents the ac impedance control of a superconducting fault current limiter (SFCL), along with the minimization of undesirable voltage spike across dc biasing coil. The nonlinear state space model of the SFCL is established with SFCL current as state variable, ac impedance as output, and dc biasing current as input variables. From this dynamic model, it is observed that the impedance can be controlled between a minimum value, when both the cores are saturated due to high dc biasing current and a maximum value when both the cores are unsaturated due to field suppression (FS) or switching off the dc biasing source. At the same time, the undesirable but inevitable voltage across dc coil due to FS can be reduced by controlling the stiffness of the dc control current. A high-frequency modified bang-bang type controller is designed and simulated. The simulation shows that the controller not only tracks the reference impedance very well, but also reduces the induced voltage across dc coil. The controlled SFCL impedance not only reduces the prospective fault current, but is also useful for relay coordination especially for impedance relays.