A 0.029-mm² 17-fJ/Conversion-Step Third-Order CT <inline-formula> <tex-math notation="LaTeX">$\Delta\Sigma$ </tex-math> </inline-formula> ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

Abstract

This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT ΔΣ ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.