Accurate Robustness Assessment of HDL Models Through Iterative Statistical Fault Injection

Abstract

Simulation-based fault injection is commonly used to assess the robustness of hardware components modelled using Hardware Description Languages (HDL). The current complexity of modern circuits usually makes not feasible the consideration of all possible combinations of fault models, targets, and times. By assuming a confidence interval and error margin, statistical fault injection exploits the principle of statistical sampling to reduce the number of experiments while keeping the results representative of the whole population of fault injections. Since the percentage of injected faults leading to failure is a priori unknown, such number of experiments is usually determined by selecting the value maximizing the sample size. This paper argues that this conservative assumption leads to a worst-case scenario that can be improved. The proposal relies on an iterative algorithm that progressively adjust the number of experiments by estimating the percentage of those leading to failure and the error of the estimation. The considered case study illustrates the feasibility and usefulness of the proposal through the robustness assessment of the LEON3 microprocessor model. Beyond that example, this research provides new means to decide when to stop a fault injection campaign and to estimate the error existing in the results finally reported.