FPGA‐SoC implementation of an ICA‐based background subtraction method

Abstract

Summary This paper presents the development and implementation of an independent component analysis (ICA)–based background subtraction method on a field programmable gate array (FPGA) system on a chip (SoC) with embedded processor. The use of the classic form of ICA for this purpose results in a complex implementation with high hardware resource usage for an embedded system. Therefore, an alternative version of FastICA was developed that adapts directly to the parallelism offered by the FPGA. In addition, the incorporation of this version of ICA into the motion‐detection method exploits the architecture of the FPGA‐SoC with embedded processor. This recent technology complements the parallelism of the FPGA with the general‐purpose computing capacity of the processors while maintaining low energy consumption and a compact size. The above features are appropriate for autonomous devices that handle mainly background subtraction, while a central device receives this information and performs the remaining tasks required for the application. The use of processors allows a faster implementation and integration of the device into other systems in a simple manner, while the parallelism of the FPGA increases the processing speed by accelerating intensive numeric calculations. The results obtained from the implementation that uses both FPGA and the embedded processor of the SoC show an increase of 3300% in the number of frames per second compared with an implementation that uses only the embedded processor.