2018 · 17 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsLow-power Digital Circuit DesignVoltage RegulatorsVoltage ScalingCurrent DensityDroop ControlLow-power Cmos DesignLow-voltage Cmos DesignRegulator DesignSettling TimeUltra-low-power CmosVoltage Scaling In Digital Circuits
In recent digital low-drop-out (LDO) regulator designs, event-driven (ED) control achieved significantly better scaling in the output capacitor and voltage droop over Time-Driven (TD) one. The state-of-the-art ED LDO design, however, still has several drawbacks including long settling time and low current density. This paper presents a new LDO based on novel self-triggering ED control and initialization. The 0.5V digital LDO in a 65 nm achieves the best-in-class performance in the droop voltage, output capacitor size, settling time, and current density over the prior ED and TD LDOs.