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Sparse Winograd Convolutional Neural Networks on Small-scale Systolic Arrays
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2019
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Convolutional Neural NetworkEngineeringMachine LearningHardware AlgorithmComputer ArchitectureArray ComputingSparse Neural NetworkParallel ComputingDense ImplementationComputer EngineeringSmall-scale Systolic ArraysComputer ScienceReconfigurable ArchitectureDeep LearningFpga DesignHardware AccelerationMassive ParallelismDomain-specific AcceleratorParallel ProgrammingSparse Winograd Convolution
The reconfigurability, energy-efficiency, and massive parallelism on FPGAs make them one of the best choices for implementing efficient deep learning accelerators. However, state-of-art implementations seldom consider the balance between high throughput of computation power and the ability of the memory subsystem to support it. In this paper, we implement a framework on FPGA by combining the sparse Winograd convolution, clusters of small-scale systolic arrays, and a tailored recursive Z-Morton memory layout design. We also provide an analytical model analysis for the general Winograd convolution algorithm as a design reference. Experimental results on various CNN models show that it achieves very high computation resource utilization, 20x~30x energy efficiency, and more than 5x speedup compared with the dense implementation.