Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers

Abstract

Due to the intensive use of discrete transforms in image/video coding, the search for fast and power-efficient design approaches for their hardware implementation becomes essential. The Discrete Tchebichef Transform (DTT) represents a discrete class of the Chebyshev orthogonal polynomials, and it is an alternative for the Discrete Cosine Transform, commonly used in picture coding. The state-of-the-art approximate DTT matrix is composed of 0, 1, -1, 2, and -2 values. In this work, we propose a new approximation for the 8-point DTT, with a higher power- and compression-efficiency by exploring coefficient truncation, leading to the values 1/16, -1/16, 1/8, and -1/8. Considering operations with integers, the smaller magnitude of coefficients causes truncation in the internal transform calculations and leads to lower values for the non-diagonal residues, which reduces non-orthogonality. The results show that the proposed 8-point pruned approximate DTT hardwired ASIC solutions increase the maximum frequency up to 64%, minimize the circuit area up to 43.6%, and saves up to 65.4% in power dissipation. The results of our DTT approximation proposal mapped for FPGA show an increase of up to 58.9% on maximum frequency, and savings of about 28.7% and 32.2% on slices and dynamic power, respectively, when compared with the literature. Our approximate DTT proposal also achieves higher compression ratio and less quality loss in the compressed image, when compared to state-of-the-art approximate DTT hardware designs.