The Design and Implementation of High-Speed Codec Based on FPGA

Abstract

This article mainly proposes a high-speed encoding and decoding method for LDPC code on FPGA. This method converts a quasi-cyclic LDPC code into a block quasi-cyclic LDPC code, and uses a similar transformation to generate a corresponding generator matrix, thereby improving the parallelism of encoder and decoder and making them have high throughput. Finally, we implemented high-speed encoding and decoding on the FPGA chip of the Kintex7 system by using the CCSDS-recommended (8176, 7154) LDPC code, and these encoder and decoder achieve a throughput of 2.97 Gbps under the condition of 5 iterations.