Low-Loss Highly Linear Integrated Passive Phase Shifters for 5G Front Ends on Bulk CMOS

Abstract

Two passive phase shifters (PSs) are proposed to minimize insertion loss (IL) in bulk CMOS technology for 28-GHz fifth generation integrated phased-array transceivers. The first PS is based on a true delay phase shift structure, where a modification is proposed to facilitate the use of larger switch size minimizing the IL in the bypass mode. The second PS is based on matched high-pass and low-pass sections to maximize the bandwidth of the phase shift. Two 3-bit passive PS prototypes, implemented in 40-nm bulk CMOS technology, are designed to be shared between the transmitter and receiver units. The first and second prototypes achieve low IL of 6 dB across 24-34and 22-36-GHz frequency ranges with root-mean-square phase error less than 13° and 12.8°, respectively. The two prototypes have input P1 dB and IIP3 higher than 8.5 and 21 dBm, respectively.