A Compact 75 GHz LNA with 20 dB Gain and 4 dB Noise Figure in 22nm FinFET CMOS Technology

Abstract

This paper presents E-band (71-76 GHz) LNA design in 22nm CMOS FinFET technology. Stacked topology with DC current re-use for 2-stage cascaded LNA results in power efficient design with high performance. Measurement shows peak gain of 20 dB and minimum noise figure of 4 dB with 10.8 mA current consumption from 1 V supply. Measured 3-dB bandwidth is 10.4 GHz and input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1dB</sub> is -22.8 dBm. The active layout area of the LNA is 0.155 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the authors' knowledge, these are the state-of-art values in terms of noise figure and DC power consumption among E-band CMOS LNAs reported in the literature.