MALOC: A Fully Pipelined FPGA Accelerator for Convolutional Neural Networks With All Layers Mapped on Chip

TLDR

FPGAs used for CNN acceleration often mimic ASIC designs that multiplex all layers onto shared hardware, underutilizing FPGA reconfigurability and reducing computational efficiency. This work introduces an FPGA architecture that assigns each CNN layer to dedicated on‑chip units, enabling fully pipelined concurrent execution. A roofline‑model‑based mapping and optimization framework is developed to maximize resource utilization and computational efficiency, and a one‑stop design tool generates the accelerator; the design is implemented on Xilinx Zynq‑7020 and Virtex‑7 690t. The accelerator achieves 910.2 GOPS on Virtex‑7 690t and 36.36 GOPS/W on Zynq‑7020, outperforming previous FPGA CNN accelerators.

Abstract

Recently, field-programmable gate arrays (FPGAs) have been widely used in the implementations of hardware accelerator for convolutional neural networks (CNNs). However, most of these existing accelerators are designed in the same idea as their ASIC counterparts, in which all operations from different layers are mapped to the same hardware units and working in a multiplexed way. This manner does not take full advantage of reconfigurability and customizability of FPGAs, resulting in a certain degree of computational efficiency degradation. In this paper, we propose a new architecture for FPGA-based CNN accelerator that maps all the layers to their own on-chip units and working concurrently as a pipeline. A comprehensive mapping and optimizing methodology based on establishing roofline model oriented optimization model is proposed, which can achieve maximum resource utilization as well as optimal computational efficiency. Besides, to ease the programming burden, we propose a design framework which can provide a one-stop function for developers to generate the accelerator with our optimizing methodology. We evaluate our proposal by implementing different modern CNN models on Xilinx Zynq-7020 and Virtex-7 690t FPGA platforms. Experimental results show that our implementations can achieve a peak performance of 910.2 GOPS on Virtex-7 690t, and 36.36 GOP/s/W energy efficiency on Zynq-7020, which are superior to the previous approaches.