A 100-MS/s–5-GS/s, 13–5-bit Nyquist-Rate Reconfigurable Time-Domain ADC

Abstract

This paper presents a 65-nm CMOS Nyquist-rate reconfigurable time-based analog-to-digital converter (ADC). The time-domain nature of the ADC allows for efficient hardware reuse and a wide range of reconfigurability. The ADC employs a reconfigurable time-to-digital converter (TDC) that can be configured as a high-resolution 1-ps correlated double sampling SAR-TDC for the high-resolution modes or as a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times $ </tex-math></inline-formula> asynchronous time-interleaved flash-TDC for the high sampling rate modes. The Nyquist-rate ADC supports continuous sampling rate variations from 100 MS/s to 5 GS/s providing 13–5-bit resolution with exponential power scaling from 8.4 to 22.3 mW, respectively. A programmable highly linear 1-bit folded voltage-controlled oscillator is employed to provide the appropriate tuning characteristics for different sampling rate modes with high linearity. The ADC linearity is further enhanced using foreground digital calibration achieving figure-of-merit ranging from 14.6 to 196 fJ/conv.