Design, implementation & comparison of vedic multipliers with conventional multiplier

Abstract

Addition, Subtraction and Multiplication are commonly used basic arithmetic operations. In these operations, Multiplication requires more processing time than other Arithmetic operations. In this paper, we will discuss various multiplication techniques. For fast multiplication, here we are using Vedic multiplication technique, which is one of the most popular multiplication technique. In this paper, comparative study of types of Vedic Multiplier and Conventional Multiplier is done. We have designed a 16-bit Multiplier using Vedic Multiplication technique (Urdhva Tiryagbhyam sutra, Nikhilam Sutra and Ekadhikena Purvena Sutra) and a conventional multiplier for generating the partial products. We have implemented the design using Verilog HDL and Synthesized & simulated using Xilinx ISE 14.2i on xc3s500e-5pq208 device.