In-Memory Computing with Memristor Arrays

Abstract

Memristors with tunable non-volatile resistance states offer the potential for in-memory computing that mitigates the von-Neumann bottleneck. We build a large scale memristor array by integrating a transistor array with Ta/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> memristors that have stable multilevel resistance states and linear IV characteristic. With off-chip peripheral driving circuits, the memristor chip is capable of high-precision analog computing and online learning. We demonstrate a weight-update scheme that provides linear and symmetric potentiation and depression with no more than two pulses for each cell. We train the array as a single-layer fully-connected feedforward neural network for the WDBC data base and achieve 98% classification accuracy. We further partition the array into a two-layer network, which achieves 91.71% classification accuracy for MNIST database experimentally. The system demonstrates high defect tolerance and excellent speed-energy efficiency.