40 nm Ultralow-Power Charge-Trap Embedded NVM Technology for IoT Applications

Abstract

A 40 nm charge-trap embedded NVM technology is presented which is operational at the main power supply of 0.81 to 1.21 V. It is based on SONOS and requires only five extra masking steps beyond standard CMOS. A product-ready 8Mb macro is used to demonstrate technology capabilities. Key features are 25 ns read access time in the 0.99 to 1.21 V supply range and very low current consumption. The macro provides several power- saving modes, 100k write cycles and 10-year data retention for application in consumer and industrial SoCs.