2018 · 15 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringEmbedded SystemsLow-power DesignMicroelectronicsCmos Circuit DesignEmbedded Memory BlocksEnergy-efficient Embedded SystemsIot Embedded SystemsLow-power Digital Circuit DesignPower ManagementCmos ScalingData RetentionEnergy-efficient Memory DesignLow-power Embedded DesignLow-power Embedded SystemsLow-voltage Cmos DesignPower Supply DesignUltra-low-power Cmos
A 40 nm charge-trap embedded NVM technology is presented which is operational at the main power supply of 0.81 to 1.21 V. It is based on SONOS and requires only five extra masking steps beyond standard CMOS. A product-ready 8Mb macro is used to demonstrate technology capabilities. Key features are 25 ns read access time in the 0.99 to 1.21 V supply range and very low current consumption. The macro provides several power- saving modes, 100k write cycles and 10-year data retention for application in consumer and industrial SoCs.
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Advancement in Charge-Trap Flash memory technology
Saied Tehrani, James Jungho Pak, Mark Randolph et al. · 2013 · 24 citations
Engineering, Computer Engineering, Electrical Engineering +15